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题目描述 实现数据位宽转换电路#xff0c;实现8bit数据输入转换为16bit数据输出。其中#xff0c;先到的8bit数据应置于输出16bit的高8位。
电路的接口如下图所示。valid_in用来指示数据输入data_in的有效性#xff0c;valid_out用来指示数据输出…整数倍数据位宽转换8to16
题目描述 实现数据位宽转换电路实现8bit数据输入转换为16bit数据输出。其中先到的8bit数据应置于输出16bit的高8位。
电路的接口如下图所示。valid_in用来指示数据输入data_in的有效性valid_out用来指示数据输出data_out的有效性clk是时钟信号rst_n是异步复位信号。 方法一
timescale 1ns/1nsmodule width_8to16(input clk , input rst_n ,input valid_in ,input [7:0] data_in ,output reg valid_out,output reg [15:0] data_out
);reg [1:0] cnt;always(posedge clk or negedge rst_n)beginif(!rst_n)cnt 2b0;else if(valid_in 1b1 cnt 2d1)cnt 2b0;else if(valid_in 1b1)cnt cnt 1b1;endreg [7:0] data_in_reg;always(posedge clk or negedge rst_n)beginif(!rst_n)data_in_reg 8b0;else if(valid_in 1b1)data_in_reg data_in;endalways(posedge clk or negedge rst_n)beginif(!rst_n)data_out 16b0;else if(valid_in 1b1 cnt 2d1)data_out {data_in_reg,data_in};endalways(posedge clk or negedge rst_n)beginif(!rst_n)valid_out 1b0;else if(valid_in 1b1 cnt 2d1 )valid_out 1b1;elsevalid_out 1b0;end
endmodule方法二
timescale 1ns/1nsmodule width_8to16(input clk , input rst_n ,input valid_in ,input [7:0] data_in ,output reg valid_out,output reg [15:0] data_out
);reg [7:0] data;parameter WAIT1 1b0;parameter WAIT2 1b1;reg cur_state;reg next_state;always(posedge clk or negedge rst_n)if(!rst_n)cur_state WAIT1;elsecur_state next_state;always(*)case (cur_state)WAIT1: beginif(data_in) beginnext_state WAIT2;end else beginnext_state WAIT1;endendWAIT2: beginif(data_in)next_state WAIT1;elsenext_state WAIT2;endendcasealways(posedge clk or negedge rst_n)if(!rst_n) begindata_out 16d0;valid_out 1b0;data 8d0;end elsecase (cur_state)WAIT1: beginif(valid_in)data data_in;valid_out 1b0;endWAIT2: beginif(valid_in) begindata_out {data, data_in};valid_out 1b1;end elsevalid_out 1b0;endendcaseendmodule
