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Generics
Generic nameTypeValueDescriptionN4
Ports
Port nameDirectionTypeDescriptionclkinputrst_ninp…重写了权重轮询仲裁添加lock输入信号表示请求方收到了仲裁许可在对应的lock拉低之前仲裁器不可以开启新的仲裁。
Generics
Generic nameTypeValueDescriptionN4
Ports
Port nameDirectionTypeDescriptionclkinputrst_ninputrequestinput[N-1:0]lockinput[N-1:0]grantoutput[N-1:0]
Verilog实现
rtl代码
timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2023/07/20 16:11:36
// Design Name:
// Module Name: round_robin_arb
//
// 功能
// -1- Round Robin 仲裁器
// -2- 仲裁请求个数N可变
// -3- 加入lock机制
// -4- 复位时的最高优先级定为 0 次优先级1 - 2 …… - N-2 - N-1
//
// module Round_Robin_Arbiter #(parameter N 4 //仲裁请求个数
) (input clk,input rst_n,input [N-1:0] request,input [N-1:0] lock,output [N-1:0] grant //one-hot
);// 存储移位后上一次仲裁结果reg aaa;wire bbb;reg [N-1:0] last_state;reg [N-1:0] grant_r;assign bbb ~|(lock grant);assign grant grant_r;always (posedge clk or negedge rst_n)if (!rst_n) aaa 0;else aaa |request ~(|(lock grant));always (posedge clk or negedge rst_n) beginif (!rst_n) last_state 4b0001; // 默认值表示最低位的优先级最高else if (aaa) last_state {grant[N-2:0], grant[N-1]}; // 有仲裁请求根据上一次的仲裁结果左移1bit后用于控制新的优先级else last_state last_state; // 无仲裁请求时pre_state不更新end// 如果最左侧几个高优先级主机都为发起仲裁请求需要从最低位开始轮询。// 此处通过两个request拼接将右侧低位拼接到左侧即可实现对低位的判断。wire [2*N-1:0] grant_ext;assign grant_ext {request, request} ~({request, request} - last_state);//得到的grant_ext必定为一个独热码但是置高位可能在代表低位的高4bit中因此进行求或运算always (posedge clk or negedge rst_n) beginif (!rst_n) begingrant_r 0;// grant_ext 0;end else if (bbb) begin// grant_ext {request,request} ~({request,request} - last_state);grant_r grant_ext[N-1:0] | grant_ext[2*N-1:N];endend// wire aaa;// assign aaa (|request ~(|(lock grant)));// wire [3:0] last_state;// assign last_state rst_n ? aaa ? {grant[N-2:0], grant[N-1]} : last_state : b0001;// assign grant bbb ? grant_ext[N-1:0] | grant_ext[2N-1:N] : grant;
endmoduletb代码
//
// 功能测试模块 Round_Robin_Arbiter 功能
// timescale 1ns / 1ps
module TB_Round_Robin_Arbiter();parameter N 4; //仲裁请求个数reg clock;
reg reset_b;
reg [N-1:0] request;
reg [N-1:0] lock;
wire [N-1:0] grant;//one-hotinitial clock 0;
always #10 clock ~clock;initial
beginreset_b 1b0;request 0;lock 0;#20;reset_b 1b1;(posedge clock)request 2;lock 2;(posedge clock)request 0;(posedge clock)request 5;lock 7;(posedge clock)lock 5;(posedge clock)request 1;(posedge clock)lock 1;(posedge clock)request 0;(posedge clock)lock 0;#40;(posedge clock)request 0;lock 2;(posedge clock)request 0;(posedge clock)request 5;lock 7;(posedge clock)lock 5;(posedge clock)request 1;(posedge clock)lock 1;(posedge clock)request 0;(posedge clock)lock 0;#100;$finish;
endRound_Robin_Arbiter #(.N(N)) inst_Round_Robin_Arbiter (.clk (clock),.rst_n (reset_b),.request (request),.lock (lock),.grant (grant));endmodule仿真结果
